With the emergence of multimedia and high-definition TVs, flat panel TV, with Plasma Display Panel (PDP) as a representative, comes into our daily lives. High-definition, digital and flat panel TVs have become the development tendency of color televisions. Because of advantages of wide viewing angle, fast response, small thickness, large screen and full digital operations, the PDP becomes an ideal display device of the high-definition digital TVs, large-size wall hung TVs and multimedia terminals, and thus has wide applications with good prospects.
With the development of the PDP to large size and high resolution, the number of driver chips required by a single screen is significantly increased, which presents requirements of multi-output and compact size for driver chips. In the PDP driver chip, high voltage devices, that output high voltages by logical control, occupy most of the area of the chip. Therefore, the design for the high voltage devices is of the greatest importance for the compact size of the chip. The performance and cost of the driver chip for the plasma display panel will directly decide the performance and cost of the PDP TV.
Document 1 (M. R. Lee, Oh-Kyong Kwon, S. S. Lee, et al., SOI High Voltage Integrated Circuit Technology for Plasma Display Panel Drivers, Proceedings of 1999 International Symposium on Power Semiconductor Devices and ICs, Vol. 11: 285-288) discloses 150V and 250V high voltage SOI integrated circuit (IC) technology using Extended Drain MOSFET (EDMOSFET) and dielectric isolation for PDP driver chips with line scanning and column addressing.
As shown in FIG. 1, the SOI IC of this technology is based on 0.8 μm CMOS and includes an n-type substrate 1, a 3 μm buried oxide layer 2 and a 5.5 μm SOI (Silicon-On-Insulator) layer 3, where HV-PMOS, HV-NMOS and LV-CMOS devices are arranged on it and are isolated from each other by dielectric isolation trenches formed by oxide layers 14 on the side walls of the trenches and filler 83 filled in the trenches. The SOI IC further includes: a deep n-type dopant well region 4; a deep p-type dopant well region 5; n-type dopant well regions 31, 32 and 34; an n-type buffer region 33; p-type dopant well regions 41, 42 and 43; n-type dopant heavily doped regions 51-54 and p-type dopant heavily doped regions 61-64 which form good ohmic contacts with metal electrode regions 91-97 respectively; a gate oxide layer 12; and polysilicon gate electrodes 81-83.
The HV-NMOS and the HV-PMOS are isolated by dielectric isolation trenches in a way of deep trench isolation in order to avoid latch-up. However, because of the relatively thick SOI layer, although the dielectric isolation SOI technology is employed, there are still large area PN junctions between the n-type dopant well region 32 and the deep p-type dopant well region 5 as well as between the p-type dopant well region 41 and the deep n-type dopant well region 4, and the advantages of low leakage current and low power consumption of the SOI technology are not put into full play; and because the deep trench dielectric isolation is employed, additional process steps such as deep trench etching, trench filling, planarization are required, which increase process cost. In addition, the withstand voltage of the buried oxide layer in the device is less than 90V/μm when the breakdown of the HV-NMOS and the HV-PMOS occurs.
Document 2 (Ming Qiao, Bo Zhang, Zhiqiang Xiao, Jian Fang, Zhaoji Li, High-Voltage Technology Based on Thin Layer SOI for Driving Plasma Display Panels, Proceedings of 2008 International Symposium on Power Semiconductor Devices and ICs, Vol. 20: 52-55) discloses a technology of thin layer SOI for PDP addressing driver circuits.
As shown in FIG. 2, the technology adopts a 2 μm buried oxide layer and a 1 μm SOI layer, and the SOI IC includes: a p-type substrate 1, a buried oxide layer 2 and an SOI layer 3, where high-voltage nLDMOS (n-channel Lateral Double-diffused MOSFET), high-voltage pLDMOS (p-channel Lateral Double-diffused MOSFET), low-voltage NMOS and low-voltage PMOS devices are arranged on the SOI layer 3 and are isolated from each other by LOCOS (Local Oxidation of Silicon). The SOI IC further includes: p-type dopant well regions 31, 33 which are used to form the body regions of the low-voltage NMOS and the high-voltage nLDMOS respectively; a p-type buffer region 32, a p-type drift region 34, n-type dopant well regions 41, 42 which are used to form the body regions of the low-voltage PMOS and the high-voltage pLDMOS respectively; an n-type buffer region 43; an n-type drift region 44; n-type dopant heavily doped regions 51-54; p-type dopant heavily doped regions 61-64; polysilicon gate electrodes 81-84; a field oxide layer 10; a p-type dopant field region 13; and LOCOS isolation regions 14.
In the above thin layer SOI technology, affected by back-gate depletion, the breakdown voltage of the pLDMOS is limited by the thickness of the SOI layer and the buried oxide layer. The buried oxide layer of the high-voltage device has a thickness of 2 μm, and when the breakdown of high-voltage nLDMOS and the high-voltage pLDMOS devices occurs, the withstand voltage of the buried oxide layer is less than 90V/μm.
Therefore, in the prior art, when the breakdown of the SOI devices occurs, the vertical withstand voltage of the buried oxide layer per unit of thickness is small.